A silicon integrated circuit has been made large-scaled and high-performanced according to the Moore's law so far and has supported an advanced information technology (IT) society in terms of hardware. It is expected that the trend will continue from now on. However, in a usual bulk CMOS circuit, scaling limit in a close future has begun to be apprehended. The main cause includes an increase of a leakage current accompanying the scaling of a transistor, a switching characteristic deterioration (an increase of a sub-threshold coefficient) of a transistor, or the like. That is, the seriousness of the problem exists in that the more progresses the technology node, the more increases the percentage of an ineffective electrical power caused by the leakage current other than an operating power.
In order to conquer this essential difficulty, it is expressed in the ITRS Road map that an ultra-thin body completely-depleted SOI (Silicon-on-Insulator) device, a double-gate/multi-gate MOSFET, or the like will be introduced in the early 2010's. Among them, especially, a Fin type double-gate MOS field-effect transistor having a standing lateral channel with a simple fabricating process of a self-aligned double gate attracts attention from the world as a promising device candidate after 32 nm node.
However, even in this double-gate MOS field-effect transistor, when a gate length of the device is reduced to 20 nm or less (corresponding to the technology after the 32 nm node), it is not easy to suppress completely the leakage current caused by short channel effect and the increase of the sub-threshold coefficient.
Because a standing Si-Fin channel 5 is formed so as to be sandwiched with a gate material 3 in a conventional fin (Fin) type double gate MOS field-effect transistor structure illustrated in FIGS. 1 to 3, the potential of the channel will be strongly controlled by a gate electrode located on both sides of the channel. Therefore, such double gate structure is effective in suppression of the leakage current between a source 7-1 and a drain 7-2. However, because gate insulation films 6-1 and 6-2 have been thinned as the device is fined, the increase of a gate leakage current caused by tunneling effect, GIDL (Gate-Induced Drain Leakage), etc. has become a problem. The sub-threshold coefficient deterioration caused by the short channel effect has also been aggravated.
In a four terminal fin type MOS field-effect transistor structure (Patent Document 1) illustrated in FIGS. 4-6 in which gates 3-1 and 3-2 are separated physically and insulated electrically, the two gate insulation films at both sides of the channel 5 become the same in thickness since the gate insulation films 6-1 and 6-2 are formed at the same time on both sides of the channel. In this case, the transistor can be operated with a fixed potential by biasing on one of the two gates and by inputting a driving signal into the other. Although a threshold voltage of the transistor can be controlled by changing the value of the fixed potential, there exists a disadvantage that the sub-threshold coefficient increases rapidly.
As a patent that solves this problem, a four terminal fin type MOS field-effect transistor having an asymmetrical gate insulation films 6-1 and 6-2 illustrated in FIGS. 7 to 9 is proposed (Patent Document 2). In this device structure, by making the control side gate insulation film 6-2 thicker than the driving side gate insulation film 6-1, the problem of rapid increase in the sub-threshold coefficient is solved, and at the same time the threshold voltage is controlled.
However, in the above-mentioned conventional fin type MOS field-effect transistor, the gate leakage current caused by the thinning of the gate insulation film, GIDL, and the deterioration of the sub-threshold coefficient accompanying the device scaling or the like is not taken into consideration. In order to improve such problems, a conventional planer type MOS field-effect transistor having a movable gate electrode illustrated in FIGS. 10 to 12 is proposed (Non-patent Documents 1 and 2).
As a feature of a device structure like this, there exists a superiority that a movable gate electrode 30 is separated from the gate insulation film 6 at the time of device standby, and hence the leakage current from the gate to the channel becomes zero because of a space 40. When a voltage is applied on the gate, the movable gate electrode 30 is attached firmly to the gate insulation film 6 by electrostatic attraction force based on a potential difference between the movable gate electrode and the channel, and an electric current flows between the source 7-1 and the drain 7-2. However, since the device structure is the same as that of a conventional single gate MOS field-effect transistor, the current drivability is inferior to that of the double gate field-effect transistor. Moreover, there exists a problem that, when the gate electrode is separated from the gate insulation film 6 (when a voltage is not applied on the gate), the leakage current between the source and the drain increases rapidly as the device is scaled down. That is, in the case of short channel, there exists a problem that the leakage current between the source and the drain increases rapidly.    [Patent Document 1] Japanese Patent Laid-Open No. 2002-270850    [Patent Document 2] Japanese Patent Laid-Open No. 2005-167163    [Non-Patent Document 1] N. Abele, et al., “Suspended-Gate MOSFET: bring new MEMS functionality into solid-state MOS transistor”, IEDM Tech. Dig., 2005, pp. 1075 to 1077.    [Non-Patent Document 2] H. Kam, et al., “A New Nano-Electrical Field Effect Transistor (NEMFET) Design for Low-Power Electronics”, IEDM Tech. Dig., 2005, pp. 477 to 480.